Method of fabricating electronic package structure with multiple electronic components

ABSTRACT

An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.

BACKGROUND 1. Technical Field

The present disclosure relates to package structures, and, moreparticularly, to a stack-type electronic package structure and a methodof fabricating the same.

2. Description of Related Art

Along with the rapid development of portable electronic products, modernproducts have been developed toward the trend of high density, highperformance and miniaturization. Accordingly, various package on package(PoP) technologies are developed in semiconductor packaging industriesto meet the requirements of high density and miniaturization.

FIG. 1 is a schematic cross-sectional view of a conventional PoPstructure 1. Referring to FIG. 1, the PoP structure 1 has: a firstsubstrate 10 having a first surface 10 a and a second surface 10 bopposite to the first surface 10 a; a first semiconductor chip 11disposed on the first surface 10 a of the first substrate 10; aplurality of solder posts 13 disposed on the first surface 10 a of thefirst substrate 10; a first encapsulant 16 formed on the first surface10 a of the first substrate 10 to encapsulate the first semiconductorchip 11 and the solder posts 13; a plurality of solder balls 15 formedon the second surface 10 b of the first substrate 10; a second substrate14 stacked on the first substrate 10 through the solder posts 13; aplurality of second semiconductor chips 12 wire-bonded to the secondsubstrate 14; and a second encapsulant 17 formed on the second substrate14 to encapsulate the second semiconductor chips 12.

Generally, there is no more space available for passive components to beadded to the PoP structure 1, and the electrical performance of the PoPstructure 1 cannot be further optimized Besides, passive components aregenerally higher than the first semiconductor chip 11 and the secondsemiconductor chips 12. As such, if a passive component is added, theheight of the PoP structure 1 will be greatly increased. For example, ifthe passive component is disposed on the first substrate 10, the heightof the solder posts 13 will be increased; otherwise, if the passivecomponent is disposed on the second substrate 14, the height of thesecond encapsulant 17 will be increased. Consequently, the PoP structure1 cannot meet the miniaturization requirement.

Therefore, there is a need to provide an electronic package structureand a fabrication method thereof so as to overcome the above-describeddrawbacks.

SUMMARY

In view of the above-described drawbacks, the present disclosureprovides an electronic package structure, which comprises: a firstcarrier having an opening; at least a first electronic componentdisposed on and electrically connected to the first carrier; a pluralityof conductive elements disposed on and electrically connected to thefirst carrier; a second carrier bonded to the conductive elements andelectrically connected to the first carrier; at least a secondelectronic component disposed on the second carrier and received in theopening of the first carrier; and a first encapsulant formed on thesecond carrier and encapsulating the second electronic component and theconductive elements.

The present disclosure further provides a method for fabricating anelectronic package structure, which comprises: providing a first carrierhaving an opening with at least a first electronic component disposed onand electrically connected to the first carrier; bonding andelectrically connecting the first carrier to a second carrier through aplurality of conductive elements with at least a second electroniccomponent disposed on the second carrier and received in the opening ofthe first carrier; and forming on the second carrier a first encapsulantencapsulating the second electronic component and the conductiveelements.

In an embodiment, the first encapsulant is further formed on the firstcarrier and encapsulates the first electronic component.

In an embodiment, the opening is positioned within an edge of the firstcarrier.

In an embodiment, the opening is positioned on a side of the firstcarrier.

In an embodiment, the opening is positioned on a corner of the firstcarrier.

In an embodiment, at least one of the first electronic component and thesecond electronic component is a package, an active component, or apassive component.

In an embodiment, the conductive elements are solder balls, copper coreballs, metal elements, circuit boards, or any combination thereof.

In an embodiment, at least one of the first carrier and the secondcarrier is a circuit structure, a lead frame, a wafer, or a carrierboard with a metal layout.

In an embodiment, the first electronic component is positioned betweenthe first carrier and the second carrier.

In an embodiment, the second electronic component is electricallyconnected to the first carrier, the second carrier or both the first andsecond carriers.

In an embodiment, the second electronic component is electricallyconnected to the first carrier through a conductor.

In an embodiment, the second carrier has at least a board served as anEMI shield.

In an embodiment, before formation of the encapsulant, a secondencapsulant is formed and encapsulates the first electronic component.

Therefore, by receiving the second electronic component such as apassive component in the opening of the first carrier, the presentdisclosure reduces the height of the electronic package structure so asto meet the miniaturization requirement.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic cross-sectional view of a conventional PoPstructure;

FIGS. 2A to 2C are schematic cross-sectional views showing a method forfabricating an electronic package structure according to a firstembodiment of the present disclosure, wherein FIG. 2B′ shows anotherembodiment of FIG. 2B, and FIGS. 2C′ and 2C″ show other embodiments ofFIG. 2C;

FIGS. 3A to 3D are schematic upper views showing various aspects of afirst carrier of FIG. 2A;

FIG. 4 is a schematic cross-sectional view of an electronic packagestructure according to a second embodiment of the present disclosure;and

FIGS. 5A and 5B are schematic cross-sectional views showing variousaspects of FIG. 2C′.

DETAILED DESCRIPTION OF EMBODIMENTS

The following illustrative embodiments are provided to illustrate thedisclosure of the present disclosure, these and other advantages andeffects can be apparent to those in the art after reading thisspecification.

It should be noted that all the drawings are not intended to limit thepresent disclosure. Various modifications and variations can be madewithout departing from the spirit of the present disclosure. Further,terms such as “first”, “second”, “on”, “a” etc. are merely forillustrative purposes and should not be construed to limit the scope ofthe present disclosure.

FIGS. 2A to 2C are schematic cross-sectional views showing a method forfabricating an electronic package structure 2 according to a firstembodiment of the present disclosure.

Referring to FIG. 2A, a first carrier 20 is provided. The first carrier20 has a first side 20 a, a second side 20 b opposite to the first side20 a, and at least an opening 201 communicating the first side 20 a andthe second side 20 b. At least a first electronic component 21 and aplurality of conductive elements 23 such as solder balls are disposed onthe first side 20 a of the first carrier 20, and a plurality of firstelectronic components 21′, 21″ are disposed on the second side 20 b ofthe first carrier 20.

In an embodiment, the first carrier 20 is a core circuit structure suchas a packaging substrate, or a coreless circuit structure, and has aplurality of circuit layers 200 such as fan-out redistribution layers.In another embodiment, the first carrier 20 is a lead frame, a wafer, ora carrier board with a metal layout (for example, low temperaturecofired ceramic (LTCC) or ferrite).

The number of the opening 201 can be one or more, and the positionthereof can be determined according to the practical need and variedcorresponding to the arrangement of the circuit layers 200. In anembodiment, the opening 201 can be positioned at a center, a peripheryor a corner of the first carrier 20 so as to increase the areautilization of the first carrier 20. FIGS. 3A to 3D are schematic upperviews showing various aspects of the first carrier 20. Referring to FIG.3A, the opening 201 is completely positioned within an edge 20 c of thefirst carrier 20. Referring to FIG. 3B, one side of the opening 201communicates with an edge 20 c of the first carrier 20, i.e., a side ofthe first carrier 20. Referring to FIG. 3C, two sides of the opening 201communicate with an edge 20 c of the first carrier 20, that is, theopening 201 is positioned on a corner of the first carrier 20. Referringto FIG. 3D, three sides of the opening 201 communicate with an edge 20 cof the first carrier 20, that is, a side portion of the first carrier 20is removed.

In an embodiment, at least one of the first electronic components 21,21′, 21″ is a package such as a chip scale package, an active componentsuch as a semiconductor chip, a passive component, such as a resistor, acapacitor or an inductor, or a combination thereof. In an embodiment,the first electronic component 21 is an active component, the firstelectronic component 21′ is a package, and the first electroniccomponent 21″ is a passive component. In an embodiment, the firstelectronic components 21, 21′ are disposed in a flip-chip manner on andelectrically connected to the circuit layers 200 through a plurality ofconductive bumps 210. In an embodiment, the conductive bumps 210 aremade of such as a solder material. In another embodiment, the firstelectronic components 21, 21′ are electrically connected to the circuitlayers 200 through bonding wires (not shown). In another embodiment, thefirst electronic component 21″ is in direct contact with the circuitlayers 200.

A second carrier 24 having at least a second electronic component 22disposed thereon is provided. In an embodiment, the second carrier 24 isa lead frame having a plurality of conductive pads 240, 240′ that areseparated from one another. The second electronic component 22 is bondedto the conductive pads 240′ so as to be electrically connected to thesecond carrier 24. In another embodiment, the second carrier 24 is acarrier carrying chips. In an embodiment, the second carrier 24 is acore circuit structure, a coreless circuit structure, a wafer, or acarrier board with a metal layout (such as LTCC or ferrite).

The second carrier 24 is optionally disposed on a supporting member 25such as a tape. In an embodiment, the second electronic component 22 isa package such as a chip scale package, an active component such as asemiconductor chip, a passive component, such as a resistor, a capacitoror an inductor, or a combination thereof. In an embodiment, the secondelectronic component 22 is a passive component.

Referring to FIG. 2B, the first carrier 20 is bonded to the conductivepads 240 of the second carrier 24 through the conductive elements 23. Assuch, the circuit layers 200 of the first carrier 20 are electricallyconnected to the second carrier 24 and the second electronic component22 is received in the opening 201 of the first carrier 20.

In another embodiment, referring to FIG. 2B′, the first carrier 20 isstacked on the second carrier 24 first and then the second electroniccomponent 22 is disposed on the conductive pads 240′ of the secondcarrier 24 and received in the opening 201 of the first carrier 20.

Referring to FIG. 2C, a first encapsulant 26 is formed on the firstcarrier 20 and the second carrier 24 (or the supporting member 25) andfilled in the opening 201 so as to encapsulate the first electroniccomponents 21, 21′, 21″, the second electronic component 22 and theconductive elements 23. Thereafter, the supporting member 25 is removed.

In an embodiment, the first encapsulant 26 is made of polyimide, a dryfilm, an epoxy resin, or a molding compound. The first encapsulant 26has a first surface 26 a and a second surface 26 b opposite to the firstsurface 26 a. The second carrier 24 is embedded in the first surface 26a of the first encapsulant 26, and the conductive pads 240 are exposedfrom the first surface 26 a of the first encapsulant 26. In anembodiment, surfaces of the conductive pads 240 are flush with the firstsurface 26 a of the first encapsulant 26. As such, a solder materialsuch as solder balls (not shown) can further be formed on the exposedsurfaces of the conductive pads 240 for bonding with an electronicdevice such as a circuit board.

Further, referring to FIG. 2C′, the conductive elements 23′ can bering-shaped circuit boards or strip-shaped circuit boards that arebonded to the circuit layers 200 and the conductive pads 240 through asolder material 23 a, thus increasing the gap between the first carrier20 and the second carrier 24 and providing sufficient space between thefirst and second carrier 20, 24 for receiving the first electroniccomponent 21. In another embodiment, referring to FIG. 2C″, theconductive elements 23″ are copper core balls or (post-shaped,block-shaped or pin-shaped) metal elements of copper or gold.

Again referring to FIG. 2C′, the second electronic component 22 iselectrically connected to the circuit layers 200 of the first carrier 20of the first carrier 20 through conductors 220 such as bonding wires orclip bars. In another embodiment, referring to FIG. 5A, the conductors220 electrically connect the circuit layers 200 of the first carrier 20and circuits 540 of the second carrier 24. The circuits 540 areelectrically connected to the conductive pads 240′. In a furtherembodiment, referring to FIG. 5B, the conductors 220 electricallyconnect side circuits 500 of the first carrier 20 and the secondelectronic component 22. In an embodiment, the conductors 220 are madeof a conductive adhesive or a solder material.

Again referring to FIG. 2C″, the second carrier 24′ further has at leasta board 241 that can be separated from or connected to the conductivepads 240, 240′ and grounded to provide an electromagnetic interference(EMI) shielding effect.

Therefore, since the second electronic component 22 (such as a passivecomponent) disposed on the second carrier 24 is received in the opening201 of the first carrier 20, the present disclosure reduces the heightof the electronic package structure 2 and meets the miniaturizationrequirement.

Further, the second carrier 24′ provides an EMI shielding effect. Inaddition, if the second carrier 24, 24′ is a lead frame or a metalboard, the heat dissipating efficiency of the electronic packagestructure 2 is improved.

Conventionally, active components and passive components are disposed onthe same substrate and electrically connected through circuits of thesubstrate. By contrast, according to the present disclosure the secondelectronic component 22 (passive component) and the first electroniccomponent 21 (active component) of the electronic package structure 2are disposed on different carriers and cannot be directly electricallyconnected through circuits of the same carrier. Through the design ofthe conductors 220, the present disclosure reduces the wiring area ofthe first carrier 20 and the second carrier 24 (for example, the I/Ocount) and reduces AC and DC impedances. Referring to FIG. 2C, if thefirst electronic component 21 is electrically through the conductiveelements 23, the conductive pads 240, and circuits (not shown) of thesecond carrier 24 to the conductive pads 240′ and the second electroniccomponent 22, the circuits between the conductive pads 240, 240′ will belonger than the circuits 540 of FIG. 5A.

FIG. 4 is a schematic cross-sectional view of an electronic packagestructure 4 according to a second embodiment of the present disclosure.

Referring to FIG. 4, before the process of FIG. 2B is performed, asecond encapsulant 47 is formed on the second side 20 b of the firstcarrier 20 to encapsulate the first electronic components 21′, 21″. Thesecond encapsulant 47 is not filled in the opening 201. Then, theprocesses of FIGS. 2B to 2C are performed to obtain the electronicpackage structure 4.

In an embodiment, the second encapsulant 47 is made of polyimide, a dryfilm, an epoxy resin or a molding compound. The first encapsulant 26 andthe second encapsulant 47 can be made of the same or differentmaterials.

Through the above-described processes, the present disclosure furtherprovides an electronic package structure 2, 4, which has: a firstcarrier 20 having at least an opening 201; a plurality of firstelectronic components 21, 21′, 21″ and a plurality of conductiveelements 23, 23′, 23″ disposed on and electrically connected to thefirst carrier 20; a second carrier 24, 24′ bonded to the conductiveelements 23 so as to be electrically connected to the first carrier 20;at least a second electronic component 22 disposed on the second carrier24, 24′ and received in the opening 201; and a first encapsulant 26formed on the first carrier 20 and the second carrier 24, 24′ andencapsulating the first electronic component 21 (and the firstelectronic components 21′, 21″), the second electronic component 22 andthe conductive elements 23, 23′, 23″.

In an embodiment, the opening 201 is positioned within an edge 20 c ofthe first carrier 20.

In an embodiment, the opening 201 is positioned on a side of the firstcarrier 20.

In an embodiment, the opening 201 is positioned on a corner of the firstcarrier 20.

In an embodiment, at least one of the first electronic components 21,21′, 21″ and the second electronic component 22 is a package, an activecomponent, a passive component, or a combination thereof.

In an embodiment, the conductive elements 23, 23′, 23″ are solder balls,copper core balls, metal elements or circuit boards.

In an embodiment, at least one of the first carrier 20 and the secondcarrier 24, 24′ is a circuit structure, a lead frame, a wafer, or acarrier board with a metal layout.

In an embodiment, the first electronic component 21 is positionedbetween the first carrier 20 and the second carrier 24.

In an embodiment, the second electronic component 22 is electricallyconnected to at least one of the first carrier 20 and the second carrier24, 24′.

In an embodiment, the second electronic component 22 is electricallyconnected to the first carrier 20 through conductors 220.

In an embodiment, the second carrier 24′ has at least a board 241 servedas an EMI shield.

In an embodiment, the electronic package structure 4 further has asecond encapsulant 47 encapsulating the first electronic components 21′,21″.

Therefore, by receiving the second electronic component such as apassive component in the opening of the first carrier, the presentdisclosure reduces the height of the electronic package structure so asto meet the miniaturization requirement.

Further, the second carrier provides an EMI shielding effect andimproves the heat dissipating efficiency of the electronic packagestructure.

The above-described descriptions of the detailed embodiments are only toillustrate the implementation according to the present disclosure, andit is not to limit the scope of the present disclosure. Accordingly, allmodifications and variations completed by those with ordinary skill inthe art should fall within the scope of present disclosure defined bythe appended claims.

1-10. (canceled) 11: A method for fabricating an electronic packagestructure, comprising: providing a first carrier having an opening withat least a first electronic component disposed on and electricallyconnected to the first carrier; bonding and electrically connecting thefirst carrier to a second carrier through a plurality of conductiveelements with at least a second electronic component received in theopening of the first carrier and disposed on the second carrier; andforming on the second carrier a first encapsulant encapsulating thesecond electronic component and the conductive elements. 12: The methodof claim 11, wherein the first encapsulant is further formed on thefirst carrier and encapsulates the first electronic component. 13: Themethod of claim 11, wherein the opening is positioned within an edge ofthe first carrier, on a side of the first carrier, or on a corner of thefirst carrier. 14: The method of claim 11, wherein at least one of thefirst electronic component and the second electronic component is apackage, an active component, or a passive component. 15: The method ofclaim 11, wherein the conductive elements are solder balls, copper coreballs, metal elements, circuit boards, or any combination thereof. 16:The method of claim 11, wherein at least one of the first carrier andthe second carrier is a circuit structure, a lead frame, a wafer, or acarrier board with a metal layout. 17: The method of claim 11, whereinthe first electronic component is positioned between the first carrierand the second carrier, and the second electronic component iselectrically connected to at least one of the first carrier and thesecond carrier. 18: The method of claim 17, further comprising providinga conductor electrically connecting the second electronic component tothe first carrier. 19: The method of claim 11, wherein the secondcarrier has at least a board served an electromagnetic interference(EMI) shield. 20: The method of claim 11, further comprising, prior toforming the first encapsulant, forming a second encapsulantencapsulating the first electronic component.